FIG. 1 illustrates circuitry for a prior art six transistor (6T) memory cell 1 for a static random access memory (SRAM). As illustrated in FIG. 1, memory cell 1 has two cross-coupled inverters 10 and 20 coupled between a supply voltage VSUPPLY node and a ground node to generate complementary signals at storage nodes 11 and 21. Inverter 10 has a pull-up p-channel field effect transistor (PFET) 12 and a pull-down n-channel FET (NFET) 14. The gates of PFET 12 and NFET 14 are both coupled to receive a signal at storage node 21 to generate an inverted signal at storage node 11. Similarly, inverter 20 has a pull-up PFET 22 and a pull-down NFET 24. The gates of PFET 22 and NFET 24 are both coupled to receive a signal at storage node 11 to generate an inverted signal at storage node 21. The complementary signals at storage nodes 11 and 21 represent a single bit value depending on which signal is at which storage node 11 or 21.
Memory cell 1 also has NFETs 16 and 26 to access memory cell 1 to read a bit value from and/or write a bit value to memory cell 1. The gate of NFET 16 is coupled to receive a signal on a word line 30 to couple storage node 11 to a bit line 31. The gate of NFET 26 is coupled to receive a signal on word line 30 to couple storage node 21 to a bit line 32. Memory cell 1 may then be accessed by sensing the complementary signals on bit lines 31 and 32 to read the bit value stored by memory cell 1 or by asserting complementary signals on bit lines 31 and 32 to write a bit value to memory cell 1. NFETs 16 and 26 are known as transfer, access, or pass transistors.
To speed reading the bit value, PFETs 41, 42, and 43 are activated in response to a signal on a precharge line 40 to precharge bit lines 31 and 32 by coupling them to a supply voltage VSUPPLY node. The bit value may then be read as soon as bit line 31 is pulled down by NFET pair 14 and 16 or bit line 32 is pulled down by NFET pair 24 and 26 without having to wait for the other bit line 32 or 31 to be pulled up.
Memory cell 1 may be designed to help meet a desired level of stability for a given memory size and process to help improve manufacturing yield. Memory cell 1 may be designed, for example, to account for mismatch in threshold voltage Vth of neighboring transistors as such mismatch reduces stability. As transistor dimensions are scaled, accounting for threshold voltage mismatch can prove challenging as the variability in the number and location of channel dopant atoms can result in restrictive electrical deviations in transistor threshold voltages Vth.
Read stability can be loosely defined as the probability that memory cell 1 will retain its stored bit value during a read operation. Memory cell 1 is susceptible to losing its stored bit value during a read operation due to a voltage bump resulting from charge sharing between a lightly loaded low storage node, such as storage node 21 for example, and a highly capacitive precharged bit line 32 when NFET 26 is activated. Memory cell 1 may lose its stored bit value if the magnitude of the voltage bump becomes larger than the trip point of inverter 10. Because such charge sharing results from the voltage division by neighboring NFETs 24 and 26 between precharged bit line 32 and ground, read stability is generally proportional to the ratio of the transconductance of NFET 24 relative to that of NFET 26.
Write stability can be loosely defined as the probability that memory cell 1 will be written with an intended bit value during a write operation. Because a write is performed by discharging the voltage at the high storage node, such as storage node 21 for example, through NFET 26, write stability is generally proportional to the ratio of the transconductance of NFET 26 relative to that of PFET 22.
Example ways to improve stability of memory cell 1 include (1) sizing pull-down NFET 14 and 24 to have an increased width at the expense of increased cell area and reduced write stability, (2) sizing access NFET 16 and 26 to have a larger channel length at the expense of reduced read current and therefore reduced read operation speed, (3) using a separate, increased supply voltage VSUPPLY at the expense of additional circuitry and increased power consumption and/or heat, and/or (4) adding a scalable negative supply voltage generator at the expense of additional circuitry to drive the source of pull-down NFET 14 and 24 to a negative voltage before word line 30 is activated to increase the strength of pull-down NFET 14 and 24.
The figures of the drawings are not necessarily drawn to scale.